The present invention relates to a magnetic memory device and a method for production thereof. The magnetic memory device is a magnetic random access memory (MRAM) of nonvolatile type consisting of memory elements each having a magnetization pinned layer in which the direction of magnetization is pinned and a magnetic layer in which the direction of magnetization is variable, with one laid on top of the other.
The recent wide spread of information and communications equipment, particularly personal small ones such as portable terminals, requires their constituents (such as memory elements and logic elements) to have improved performance, including high integration, high speed, and low power consumption.
Particularly, non-volatile memory is regarded as indispensable in the age of ubiquitous computing because it preserves personal important information in case of dead battery and network failure or server breakdown. Recent portable equipment is so designed as to reduce power consumption as much as possible by keeping idle circuit blocks in stand-by mode. It would be possible to save power and memory if a non-volatile memory functioning as both high-speed work memory and high-capacity storage memory is realized. It would make the “instant-on function” feasible which permits equipment to start working instantly as soon as power is turned on.
Among non-volatile memory are flush memory, which relies on semiconductors, and FRAM (ferroelectric random access memory), which relies on ferroelectric substances.
Flush memory is limited in writing speed to the order of microseconds. FRAM is also limited in the number of rewriting cycles to 1012 to 1014, that is, it is too poor in endurance to replace SRAM (static random access memory) and DRAM (dynamic random access memory). Moreover, it presents difficulties in microprocessing of ferroelectric capacitors therein.
There is noteworthy non-volatile memory free of these disadvantages, which is magnetic memory called MRAM (Magnetic Random Access Memory). MRAM in the early stage is one which is based on spin valve. It utilizes the AMR (Anisotropic Magneto Resistive) effect, which was reported by J. M. Daughton in “Thin Solid Films”, vol 216 (1992), pp. 162 to 168. Alternatively, it utilizes the GMR (Giant Magneto Resistance) effect, which was reported by D. D. Tang et al. in “IEDM Technical Digest” (1997), pp. 995 to 997. Unfortunately, they have the disadvantage that the memory cell has a low resistance of 10-100Ω which leads to a large power consumption per bit for reading. This disadvantage makes it difficult to realize a large-capacity memory.
There is another type of MRAM which utilizes the TMR (Tunnel Magneto Resistance) effect. It has come to attract attention because of its remarkable increase in the rate of change in resistance from 1 to 2% at room temperature (as reported by R. Meservey et al. in “Physics Reports”, vol. 238, pp. 214 to 217, 1994) to nearly 20% (as reported by T. Miyazaki et al. in “J. Magnetism & Magnetic Material”, vol. 139, (L231), 1995).
MRAM is a semiconductor magnetic memory that relies on the magnetoresistance effect resulting from spin dependent conduction of nanomagnetic substances. It is a non-volatile memory that retains memory without external power supply.
MRAM has such a simple structure that it can be highly integrated with ease. It is capable of rewriting many times because it relies on the rotation of magnetic moment for recording. It is also expected to have a very high access speed. In fact, its ability to run at 100 MHz has been reported by R. Scheuerlein et al. in ISSCC Digest of Technical Papers, pp. 128 to 129, Feb. 2000.
MRAM is broadly divided into two types. One is cross-point type and the other is 1T1J type or 2T2J type. MRAM of cross-point type is disclosed in U.S. Pat. No. 5,640,343. MRAM of 1T1J type consists of one selecting element and one TMR element. MRAM of 2T2J consists of two selecting elements and two TMR elements which are complementary to each other.
The MRAM consisting of one selecting element and one TMR element is shown in FIG. 33. The memory cell (or memory element) of MRAM is the TMR element 10, which consists mainly of a supporting substrate 9 and a memory layer 2 (in which the direction of magnetization rotates comparatively easily) and two magnetization pinned layers 4 and 6.
The magnetization pinned layer consists of a first magnetization pinned layer 4 and a second magnetization pinned layer 6. Between these two layers is interposed a conducting layer 5 through which they are coupled antiferromagnetically.
The memory layer 2 and the magnetization pinned layers 4 and 6 are formed from a ferromagnetic material such as nickel, iron, cobalt, and alloys thereof. The conducting layer is formed from any of ruthenium, copper, chromium, gold, and silver. The second magnetization pinned layer 6 is in contact with the antiferromagnetic material layer 7, so that it has a strong unidirectional magnetic anisotropy due to exchange interaction between these layers. The antiferromagnetic material layer 7 may be formed from a manganese alloy with iron, nickel, platinum, iridium, or rhodium, or a cobalt oxide or nickel oxide.
Between the memory layer 2 (which is a magnetic layer) and the first magnetization pinned layer 4 is interposed a tunnel barrier layer 3 formed from an insulating material such as an oxide or nitride of aluminum, magnesium, or silicon. It cuts off the magnetic coupling between the memory layer 2 and the magnetic pinned layer 4, and it also permits tunnel current to flow. The magnetic layer and the conductor film are formed mainly by sputtering. The tunnel barrier layer 3 may be formed by oxidizing or nitriding the metal film which has been formed by sputtering. The top coat layer 1 prevents mutual diffusion between the TMR element 10 and the wiring connected thereto. It also reduces contact resistance and protects the memory layer 2 from oxidation. It is usually formed from Cu, Ta, or TiN. The underlying electrode layer 8 serves for connection between the TMR element and a switching element connected thereto in series. This underlying layer 8 may function also as the antiferromagnetic layer 7.
The memory cell constructed as mentioned above reads information by detecting the change in tunnel current due to magnetoresistance effect (which will be described later). The magnetoresistance effect depends on the relative direction of magnetization of the memory layer and the magnetization pinned layer.
FIG. 34 is a partly simplified enlarged perspective view of an ordinary MRAM, with reading circuits omitted for brevity. This MRAM has nine memory cells and mutually intersecting bit lines 11 and writing word lines 12. Each TMR element 10 is placed at the point of intersection. Writing into the TMR element 10 is accomplished by applying current to the bit line 11 and the writing word line 12 simultaneously so that the two currents produce a combined magnetic field which changes the direction of magnetization of the magnetic layer 2 of the TMR element 10 parallel or antiparallel with respect to the magnetization pinned layer.
FIG. 35 is a schematic sectional view showing a memory cell which has a four-layered metal wiring. This memory cell is composed a reading n-type field effect transistor 19, a writing word line 12, a TMR element 10, and a bit line 11, which are arranged one over another. The field effect transistor 19 is composed of, for example, a p-type silicon semiconductor substrate 13 and a p-type well region 14 formed thereon, in which are formed a gate insulating film 15, a gate electrode 16, a source region 17, and a drain region 18. To the source region 17 is connected to a sense line through a source electrode 20. The field effect transistor 19 functions as a switching element for reading. The reading wiring 22 leading out between the word line 12 and the TMR element 10 is connected to the drain region 18 through the contact plugs 27a to 27c and the landing pads 28a to 28c in the insulating layers 29a to 29g of laminate structure placed between the reading wiring 22 and a drain electrode 23. Incidentally, the transistor 19 may be an n-type or p-type field effect transistor or any other switching element such as diode, bipolar transistor, and MESFET (metal semiconductor field effect transistor).
FIG. 36 is an equivalent circuit diagram of MRAM. It is assumed that this MRAM has six memory cells and mutually intersecting bit lines 11 and writing word lines 12. At each point of intersection are arranged a memory element 10 and a field effect transistor 19 connected thereto. The field effect transistor 19 is connected also to a sense line 21 so that it selects the element at the time of reading. The sense line 21 is connected to a sense amplifier 21b, so that stored information is detected. There are also shown a bidirectioal current drive circuit 24 for the writing word line and a current drive circuit 25 for the bit line.
FIG. 37 is an asteroid curve showing the writing condition for MRAM. It represents the reversal threshold value in the direction of magnetization of the memory layer by the magnetic field HEA applied in the direction of easy axis and the magnetic field HHA applied in the direction of hard axis. The combined magnetic field vector outside the asteroid curve brings about the reversal of magnetic field. By contrast, the combined magnetic field vector within the asteroid curve does not reverse the cell from one bistable state into the other. Any cell which is not at the intersection of the word line and the bit line receives the magnetic field generated individually by them, and it has its direction of magnetization reversed if the magnitude of the magnetic field is larger than the one-direction reversal magnetic field Hk. Consequently, only if the combined magnetic field is in the gray area, the selected cell permits selective writing.
As mentioned above, MRAM usually performs writing by means of two writing lines (the bit line and the word line), which reverse the magnetic spin in a specified cell owing to the characteristics of asteroid magnetization reversal. The combined magnetization in a single memory region is determined by the vector synthesis of the magnetic field HEA in the direction of easy axis and the magnetic field HHA in the direction of hard axis, both applied to the memory region. Current flowing through the bit line applies to the cell the magnetic field HEA in the direction of easy axis, and current flowing through the writing word line applies to the cell the magnetic field HHA in the direction of hard axis.
FIG. 38 illustrates the reading action by MRAM. Each TMR element 10 in MRAM is of layer structure as schematically shown. The magnetization pinned layer (mentioned above) is represented by a single layer 26, and other layers are omitted except for the memory layer 2 and the tunnel barrier layer 3.
As mentioned above, the writing of information is accomplished by applying current to the bit lines 11 and word lines 12 which are arranged in a matrix pattern. Current applied to these lines produces a combined magnetic field at the point of their intersection, thereby reversing the magnetic spin of the cell. The direction of magnetic spin represents either “1” or “0” as information. The reading of information is accomplished by using TMR effect resulting from magnetoresistance effect. TMR effect is a phenomenon that resistance varies depending on the direction of magnetic spin. High resistance (with the magnetic spin antiparallel) represents “1” and low resistance (with the magnetic spin parallel) represents “0”. The reading of information is accomplished as follows. Reading current (tunnel current) is applied across the word line 12 and the bit line 11, and output in proportion to resistance is detected by the sense line 21 through the field effect transistor 19 for reading.
In the case of MRAM consisting of one selecting element and one TMR element as shown in FIG. 35, it is necessary to electrically insulate the TMR element 10 by an insulating layer from the writing word line 12 (referred to as word line for short hereinafter) which intersects with the bit line 11. This makes it necessary to provide connecting holes for connection between the reading wiring 22 and other wiring layers (lower or upper layers). Moreover, there should be a certain distance between the word line 12 and the landing pad 28c in the same layer. Therefore, the size of the memory cell of the MRAM cannot be equal to or smaller than 8F2.
In other words, even though the TMR element 10 shown in FIG. 39 has an aspect ratio of 1:1 (A:B), the size of the memory cell of the MRAM cannot be equal to or smaller than 8F2 (or 2F×4F) in the direction of the bit line. (The aspect ratio of 1:1 means that the TMR element 10 is approximately round and 3F is reduced to 2F in the direction in which it intersects with the bit line 11.) However, as mentioned later, it is necessary that the shape of the TMR element 10 should be elongated in the direction in which it intersects with the bit line 11. Therefore, it becomes an ellipse with an aspect ratio of 1:2, as shown in FIG. 39.
As mentioned above, there has been proposed means to solve problems with MRAM of such structure that the lower layer wiring exists in the same layer as the word line. (Refer to U.S. Pat. No. 5,940,319 (p. 5, column 5, lines 45 to 56, and FIG. 10).) However, the proposed means for solution is not necessarily satisfactory.
FIG. 39 is a schematic diagram showing a conventional MRAM (of 1T1J type) consisting of one selecting element and one TMR element. FIG. 39A is a partial plan view, and FIG. 39B is a sectional view taken along the line b-b in FIG. 39A. As shown in FIG. 39B, the word line 12 is electrically insulated from the TMR element 10 by an insulating layer (not shown). The TMR element 10, which is connected to the bit line 11, is connected to the landing pad 28, which is arranged on the same layer as the word line 12, through the reading wiring 22. This landing pad 28 is further connected to the lower layer wiring 30 through the plug 27.
FIG. 39 shows the size of the memory cell of the MRAM. As FIG. 39A shows in plan, there should be a distance of F/2 between the boundary C of adjacent memory cells and the landing pad 28, between the boundary C of adjacent memory cells and the word line 12, and between the landing pad 28 and the word line 12. Therefore, a length of 4F is necessary in the direction along the bit line 11. On the other hand, a width of 3F is necessary in the direction of intersection with the bit line 11. (The width of 3F is a sum of the distance F/2 between the boundary C of adjacent memory cells and the width (2F) of the bit line 11.) In actual, the TMR element 10 is formed elliptic, such that the aspect ratio A:B (where A is the minor axis of ellipse and B is the major axis of ellipse) is 1:2 from the standpoint of easy magnetization. Therefore, the length in the direction of intersection with the bit line 11 cannot be made smaller than 3F.
In brief, the memory layer of the TMR element practically has its direction of energetically stable magnetic moment determined by its shape anisotropy. Therefore, it is necessary that the aspect ratio of the TMR element pattern should be larger than 2 so that the reversal of magnetization takes place with a minimum of variation. The result is that the cell size cannot be made smaller than 12F2, which is calculated from (F+3F)×(2F+F), where F is the shorter side of TMR element and 2F is the longer side of TMR element. In this case, a space of F/2 should be provided between the side of the landing pad 28 and the word line and between the side of the landing pad 28 and the hole (not shown) for connection of the reading wiring 22 to the lower layer wiring 30. (The second space is equivalent to the width of the plug 27.) That is, the distance between the word line 12 and the connecting hole should be F.